Synopsys and Cadence: The $160B Unsung Giants of Semiconductor Design

Discussing the role of EDA in AI infrastructure and chip design

This piece is written in collaboration with Calvin Zeng.

Business Overview

Cadence and Synopsys are providers of EDA design software for the semis industry, a critical and highly value-add piece of the chip design workflow. Both are well positioned to capitalize on the durable growth trends of growing chip complexity, expansion of in-house ASIC design teams, and the AI capex cycle boom and will grow at 15-20%+ CAGRs over the next 5 years, which is significantly above the overall growth of the semiconductor industry.

Cadence and Synopsys are some of the most durable, attractive businesses in all of software and technology.

Technology Overview

Cadence and Synopsys are providers of EDA (electronic design automation) software. These are a set of tools that simulates the circuits of a semiconductor chip – an evolution of the past, when hardware architects used to sketch chip designs by hand. EDA tools are critical to the chip design process, and complexity / opportunity for value-add is ever increasing with the growing complexity of semiconductor chip design.

As a brief history of EDA, large vertically integrated OEMs (e.g., Bell, TI, Intel, RCA) employed large teams of software engineers to develop similar tools in-house in the 1960s. This was when the format used to represent IC layouts, GDS (Graphic Design System) was first created as a standard. In the 1980s, the commercial ASIC industry started to rise, and with it, the rise of new design houses (e.g., LSI Logic and VLSI) that didn’t have the resources to spin up their internal chip design solution. With a burgeoning new market hungry for design tools, many of the internal captive teams at large OEMs splintered off to start EDA providers. This created a landscape of point solutions, which then saw a wave of consolidation in the latter part of the 1980s into broad suites. Today, there exists three EDA providers - Synopsys, Cadence, and Mentor (now Siemens EDA). Fast forward to today, and these three represent most of the EDA market (Cadence / Synopsys at ~30-35% mkt share, Siemens at ~10-15%, and a broader set of smaller point / specialized solutions at ~25%).

It's important to understand that EDA software is less of a “one-stop-shop” for chip design and more of a massive set of chip design tools that are loosely integrated that attack different pain points in the chip design process, which can widely vary by application, industry, and node size. There are broadly 3 categories of tools - simulation, design, and verification.

The workflow above shows the broad steps of the chip design process. The first step is specification and design, where designers define the specification / requirements of the IC and create a circuit diagram (a graphical, high-level representation of an IC). This is where the first touchpoint of EDA tools occurs.

A circuit diagram is not a physical board layout but rather a higher-level representation of the logic behind the chip. Simulation EDA tools take this proposed diagram and predict its results before it is developed, effectively modeling how a real version of this circuit would perform. This step is highly important, as it helps check for any feasibility issues before the labor-intensive process of designing the chip.

After the circuit diagram is fleshed out and tested, the next step of the chip design workflow is logic, circuit, and layout design, where this diagram is transformed into the collection of physical circuit elements that will implement that function. This is where the next set of EDA tools, Design EDA tools, help with both the logical process (assemble and connect the circuit elements) and physical process (create the interconnected geometric shapes that will implement the circuit during manufacturing).

After this actual chip design is created, the chip must be tested to see if the circuit works and can be reliably manufactured.

Verification EDA tools examining the chip’s design to ensure all components are correctly connected and optimize the layout to produce the best performance. This is accompanied by DFM (design for manufacturing) tools, where PDKs from fabs play a big role in making sure that the design can meet the requirements of the manufacturing process. This PDK layer is part of our TSMC thesis where the design ecosystem around DFM and PDKs stands far above its competitors and represents a competitive moat on top of its raw manufacturing capabilities.

Across all these sets of tools, there are broader workflow / productivity tools that make things like collaboration, traceability, and IP security more automated for the broader design team.

After the chip design layout is finalized, the production steps (mask, wafer fab, packaging, testing , assembly, and integration) start.

Business Model

Both Cadence and Synopsys make most of their revenue through subscription-based sales of their software suite. They both have a very opaque pricing process, but I’ve been able to piece together roughly the variations of pricing but note that there seems to be a lot of highly customized and bespoke agreements between individual customers.

The most common pricing scheme is seat-based pricing. These are fixed length contracts (generally 3 years) that give a certain # of licenses to a specific set of tools (e.g., 5 simulation licenses, 3 design licenses, 1 verification license, each at their own price points). Pricing is very bespoke based on the tools needed (again, EDA is less a broad software suite and more a set of tools) where there is some element of a price sheet that helps price the overall package.

For select large customers, EDA vendors sometimes do full-service pricing. This is essentially an all-you-can-eat offering with an unlimited number of seats / no restriction on toolset offered. These are likely complex contract negotiations driven by the individual relationship, expected tool use / seat growth, and customer health / willingness to pay.

“Synopsys offered Intel all you can eat for a fixed price. And that price is north of $1 billion. Samsung, again, 8 years ago, reached a similar agreement with Mentor Graphics, all you can eat.”

– Director of Semis at Azure (Feb 2021)

We expect the contracts with the largest design houses (e.g., NVDA, AMD, AVGO) to be similar and would expect corresponding price increases with their respective R&D budgets which are currently inflecting with the AI capex investment cycle.

For shorter-term engagements or as an addendum to the standard seat-based pricing, EDA vendors sometimes use a token-based pricing model. In this, customers pay upfront for a specific # of tokens which can be flexibly used for different tools on an as-needed basis. Consumption of these tokens tend to be tied to projects and represent an upsell motion where each design project requires a slightly different set of tools (therefore consuming tokens) or IP (part of both company’s IP business).

This is an opportunity to upsell additional products to the customers, and I expect consistent token-based spend to translate into price increases for larger contracts in the next renewal cycle. Again, with the growing complexity of chip design and both company’s investment in AI tools (discussed later), I think this upsell motion has many legs and will continue to drive top-line growth for both companies.

“The licenses are where the salespeople in Cadence can get very creative to maximize the value. Most of these licenses are essentially product based, is thing number one. A simple chip design, for example, has three or maybe four major steps. You have a schematic license, you need a layout license to do the layout, and maybe you need some verification to license to do some verifications.

These are the broad categories, but I'll keep it simple. A schematic engineer will use one schematic license, a layout engineer will use another one and the verification guy will use probably the third license. The cost of these licenses will be different, et cetera. The discounting structure will be different as well.

But in simple words that's how the licensing would be structured, both Cadence and Synopsys, I think what they also tend to do is they also tend to offer their customers some flexibility and that allows them to perhaps leverage or grow some of these ETUs as well. What they will do is, if there's a big customer, they'll talk to them and say, okay, you've got 10 schematic engineers, 10 layout engineers, 10 verification engineers, fine, but we understand that maybe you want to have a flexible pool of licenses also.

And this flexible pool could help you support some of the technology which you don't own at the moment from us, maybe you're using some other vendor tool for these things or maybe even some new-and-upcoming technologies, which you haven't adopted so far, et cetera, which can be added.”

– Former Sales Director at CDNS (June 2023)

Taking all of these pricing schemes into account, I think the net result is that EDA revenue is largely tied to # of chip designers employed (per seat fee) and flexes up on increasing complexity of the chip (# of tools needed at higher price points) and IP requirements (upsell of their IP offerings).

We have a good sense of the skyrocketing cost of chip design from ARM’s S1 where very large jumps occurred at the recent nodes (EUV transition) and is expected to make another large jump at 2N with the transition to GAA.

Because of the leverage to the industry trends of increasing chip complexity and growth in chip designer HC (roughly, more transistors = larger team of design engineers and more SW to run an increasing # of simulations to verify the design), both CDNS and SNPS have been able to grow consistently at ~10-15% yearly over the next 10 years.

As a top-down view of the broader industry, EDA & IP captures 2-3% of semiconductor spend.

A commonly cited barometer for EDA spend is the continual growth in the R&D budget across semis design companies. We’ve benchmarked CDNS / SNPS revenue against R&D spend of the 5 largest semis companies and found it to be a good rough heuristic, with CDNS and SNPS software spend growing to 30% of top 5 semi R&D.

An uptick in R&D spend starting 2021 corresponded with a similar rise in growth rates. With the AI race and associated Capex cycle kicking off, R&D budgets are continually being revised upwards (I think Street estimates across the board are too low on R&D based on my work on NVDA / AMD). EDA has also been capturing an increasing % of R&D spend (though this may be skewed by the entrants of hyperscalers / autos creating their own internal design teams).

Cadence vs. Synopsys

It is worth noting at this point that Cadence and Synopsys are very similar in what they provide. Most large customers are customers of both, creating a best-of-breed toolset from the broader SNPS / CDNS / Mentor product suite and using each to play pricing off each other.

“Yes, NVIDIA uses both. Yes. All these guys. They want to keep it to equal within the company because that gives them price. These are platform players. They have everything. They really want to keep everyone equal. It's not easy, by the way, because there are some good tools that Cadence have, and Synopsys doesn't have. There's some stuff that Synopsys had, which Cadence doesn't have. But in the aggregate, they try to keep them 50-50 or close.”

– CMO and SVP of Enterprise Marketing at Synopsys (March 2023)

There is some degree of preferences based on specific industry verticals, or the subclass of the toolset where one provider may be favored over the other, but in general the market share between the EDA players tends to be quite entrenched.

“So a lot of it comes down to relationships and types of designs that you're doing. So if you look at it from industry segment, historically, Cadence was always very strong in networking and in computing. So if you look at the companies in Taiwan, for example that build a lot of computers they tended to always use the Cadence piece printed circuit board tools, whereas if you look at automotive and mil-aero, historically, they have always used the Siemens tool set. So some of it breaks down by industry and a lot of it is just historical.” – VP of Engineering at CDNS (Mar 2024)

As a result of the stable market share / competitive dynamic, overlapping customer base, and similarity in product offering, the share price performance of both CDNS and SNPS are highly correlated.

The biggest difference comes from their relative valuations, where CDNS trades at a premium (~48x P/E) vs. SNPS (~42x P/E) due to its higher operating margin (~30% vs. ~20-25%). This is largely because SNPS has a larger lower-margin IP business (~25% vs. the ~10% of SNPS).

We don’t really have a hard view on whether the IP business makes SNPS a better or worse buy than CDNS. My view is that IP is a natural extension of the design product that is offered, and that alongside growing chip complexity is a greater need for off-the-shelf IP, especially as design costs at the leading edge grow higher – so I’d expect the IP revenue of both to grow in-line with their broader EDA recurring SW revenue.

In theory, with the move to chiplet architectures, the IP portfolio of Synopsys may see higher ROI as IP will no longer need to be constantly updated for the leading-edge as you should be able to mix-and-match IP at different nodes in the design of a chiplet-based IC. That being said, I think that’s a small part of the overall thesis and absent any further developments, I think that both stock prices will be highly correlated.

Cadence Overview

Cadence was founded in 1987 and segments their business into functional verification, digital IC (digital), custom IC (analog), system design, and semiconductor IP. They have roughly ~85% recurring revenue with ~$4B in 2023 revenue, growing at ~12% CAGR over the last 5 years.

They notably have a smaller IP portfolio than Synopsys and tend to focus on it less than their core EDA software portfolio. They tend to focus on differentiated IP, with an example being their recent acquisition of Rambus’ leading-edge SerDes IP assets.

“In Cadence's business we have some IP, we focus on differentiated IP, because the important thing there for us is just to have a seat at the table. It's the least profitable business at Cadence. It's about 10% of the business.” – CEO, 2023 Nasdaq Investor Conference (Dec 2023)

Cadence’s AI offering is called Cadence.AI, which is a set of tools that help automate PCB design, chip design flow, among others.

“Over the year, we have continued building out our generative Cadence.AI portfolio, the industry's broadest AI offerings, spanning chip to board to system and delivering exceptional optimization and productivity benefits. Earlier in Q2, we introduced Virtuoso Studio and Allegro X AI, bringing AI to custom/analog and PCB designs. And in Q4, we added Voltus InsightAI for automatically addressing voltage drop violations. We also pioneered bringing LLM capabilities to chip design, successfully helping Renesas accelerate functional specification to final design. Accelerating momentum of our Cadence.AI portfolio has led to an almost tenfold increase in the number of customers adopting our GenAI solutions in 2023 as customers embrace the technology to develop optimized products much more efficiently.” – CEO, Q4 2023 Earnings Call

Synopsys Overview

Synopsys was founded in 1986 and segments their business into design revenue (~65%), IP (~25%), and its application software testing business (~10%, currently in a sale process).

Unlike Cadence, Synopsys has aggressively invested in their IP licensing business. They have a much broader portfolio of IP blueprints, largely built through acquisitions and has translated into the largest licensor of IP, overtaking ARM – though they still lag behind significantly in royalties.

Their AI software suite is called Synopsys.ai, which is a set of tools focused around optimizing specific pieces of the EDA workflow (e.g., verification of design spaces, power flow, etc.). It generally feels more fleshed out than Cadence’s competing offering, though it may be due to a more promotional stance that the company takes towards their AI offering.

“Now you look at that equation, what we have been seeing consistently with those customers is about a 20% uplift in revenue when they adopt DSO.ai. And that's 20% uplift in revenue that where AI applies, meaning DSO.ai, it applies for the digital portion of the chip. So it's -- you take Fusion Compiler, that's the tool they use, they layer DSO.ai, you get 20% more spend revenue from the customer by enabling DSO.ai.

As I said, we have monetization happening today. We believe that will contribute to roughly a growth from a 12% to 14%, which is a plus 2% due to AI, where the customers are willing to pay for that technology and differentiation because it helps them reduce their time to design the chip and their ability to design a differentiated system or a chip. It depends on the application.” – CEO, Synopsys Investor Day 2023

Key Debates

1. FY24-27 / LT Growth

The biggest debate is around whether we will see a return to ~15-20% growth rates that they experienced in the COVID period or back to the historical ~10-15% growth (currently being modeled by Street). This was a part of the reaction to the somewhat disappointing FY24 guidance by Cadence which triggered a ~5x re-rating down on both stocks in early March.

We believe stronger for longer growth rates. The industry trends that drove the increased spend on CDNS / SNPS are not ebbing and in many ways are only intensifying. This is furthermore juxtaposed against a massive AI capex and demand cycle that has many trickle-down effects on the R&D budgets of chip designers. Autos, though small right now, is the next leg of design activity that should significantly pick up in the latter half of this decade with OEMs investing in custom ASIC designs.

On the complexity of chips, we have a pretty clear roadmap to GAA / CFET (3D-stacked <1N transistors) over the next decade that will continue to drive complexity / design costs up at the leading edge. We also have a wave of incoming chip innovations (e.g., 3D chiplet architecture, backside power, etc.) that will continually increase the design complexity and provide more opportunities for upsell / pricing increases of higher value add SW tools in the EDA process flow. In general – it is cheaper for a customer to invest in productivity-enhancing technology rather than hire more chip designers and I’d expect EDA to capture a growing % of the R&D budget as the AI offerings continue to get fleshed out.

“So anytime there is a new technology, in this case, the GAA, the N2, the 18A, and maybe you heard Intel earlier today talking about 14A, that's a fantastic opportunity for two reasons. In order for the customer to be able to explore that process technology innovation, even if they want to get a feel, do they want to move in that direction or not? Does it add value in terms of performance, power, et cetera? That technology, that process technology needs to be enabled.

In order to be enabled, it means Synopsys needs to design its IP on that process technology and make sure that our EDA products are comprehending that new technology in order to deliver to the target performance power area of this process technology.”

 – SNPS CEO, Q1 2024 Earnings Call

On custom silicon – companies are increasingly spinning up their own design arms (e.g., all the hyperscalers’ AI projects, TSLA / autos companies) that will create new EDA software seats. I won’t harp on this too much given our existing body of work on this subject, but ASICs and more specialized chip design that are married to SW development are key to keeping up with Moore’s law as highly generalizable chips start to fall behind on the power / efficiency curve, especially with the power / durability demands of autos and compute demands of AI. It’s clear that many companies now view in-house design capabilities alongside their SW capabilities as a necessity to stay competitive. This increases both the number of projects as well as the # of chip designers.

“[QUESTION] You’re benefiting from the emergence, right, of the custom chip or ASIC chip design adoption by the large cloud titans, large compute networking, industrial auto OEMs, right, Google, Microsoft, Meta, Cisco, Apple, Nokia, Ericsson, right? All these guys have amassed significant design teams, engaged on a lot of their own chip design activity.

But just to give some color, all the names that you mentioned are, of course, close customers. And it's been quite remarkable how system companies that in the past were very much software-only, are starting to push down, and they all realize the same thing.

The game is won at the intersection between software and hardware. Because at this point in time, we have long passed beyond the early days where hardware was built and then once you have that, you do software on top. Now, it's almost flipped over.”

 – SNPS CEO, Citi 2023 Tech Conference (Sep 2023)

While the chip complexity trend has been going on for a while now, the trends around in-house ASIC design work accelerated in 2023 and will only continue to grow in importance over the next decade. That, alongside design complexity, will drive in my view ~15-20% LT growth rates above Street which sees a return to the 2017-2020 historical norm.

2. AI Impact

We’ve already touched on the impact of AI capex spend as a big driver of semis spend, associated R&D budget, and therefore EDA spend. I also think that the investment in AI (both models and compute infrastructure) will be very beneficial for the value-add of the EDA product suite and corresponding pricing.

Both Synopsys and Cadence, over the last year, have both been promoting their LLM-driven offering, bundling up their AI products into “AI-named” product suites and hinting at potential revenue uplift from upsell of these products (Synopsys is more promotional than Cadence, citing a 20%).

I’m a bit mixed on the near-term immediate impact of LLMs on their ability to drive meaningful pricing increases. We’re still in the early stages of commercial viability of LLMs as CoPilots (see MSFT Copilot reception and development). Over the long-run, I think there is a place for a chip design CoPilot that can help chip designers in their task, but I don’t think it is nearly as revolutionary or lead to as much productivity improvements given the specialized and highly technical nature of chip design. LLMs are good for broad generalizable tasks – less so at very specific and precise knowledge.

The place where I’m more enthusiastic about is the innovations in compute infrastructure that is occurring. Many of the highest value adds in the chip design workflow come from optimization tools – often big data / reinforcement-learning problems that are very compute intensive. We are already seeing innovations in the DFM process with cuLitho, NVDA’s computational lithography program.

“Computational lithography is the most compute-intensive workload in the semiconductor manufacturing process, consuming tens of billions of hours per year on CPUs. A typical mask set for a chip — a key step in its production — could take 30 million or more hours of CPU compute time, necessitating large data centers within semiconductor foundries. With accelerated computing, 350 NVIDIA H100 systems can now replace 40,000 CPU systems, accelerating production time, while reducing costs, space and power.

“Our work with NVIDIA to integrate GPU-accelerated computing in the TSMC workflow has resulted in great leaps in performance, dramatic throughput improvement, shortened cycle time and reduced power requirements,” said Dr. C.C. Wei, CEO of TSMC. “We are moving NVIDIA cuLitho into production at TSMC, leveraging this computational lithography technology to drive a critical component of semiconductor scaling.”

Since its introduction last year, cuLitho has enabled TSMC to open new opportunities for innovative patterning technologies. In testing cuLitho on shared workflows, the companies jointly realized a 45x speedup of curvilinear flows and a nearly 60x improvement on more traditional Manhattan-style flows.”

I think that alongside GenAI is a huge amount of drag-along investment in the infrastructure and ecosystem of AI, which Synopsys and Cadence can benefit from to develop tools that further optimize the chip design process that represent hard ROI and will drive continual, justified pricing increases. Skimming through the “AI” product portfolio, it’s clear that both are investing heavily in it as behind the surface-level CoPilot tools is a broader suite of deep-learning tools that further optimize the chip design process.

3. China

China is ~18% of CDNS rev and ~16% of SNPS rev and continues to remain a key question given the sustainability of the spend coming from that region. While the actual export restrictions have been limited (the biggest impact was Huawei being cut off as a customer), China is trying to invest in their EDA ecosystem with Empyrean being the largest domestic EDA vendor, though they are still very small compared to both SNPS and CDNS. My view is that the China risk is minimal as EDA tools are extremely complex and still growing in complexity and any domestic tools are unlikely to catch up.

Furthermore, I think that the risk of export restrictions is low as the exports are very ostensibly focused on specific capabilities (e.g., AI) or in the manufacturing capabilities (e.g., no EUV for China). I generally agree with Cadence’s CEO’s remarks at the Wells Fargo conference.

“If you look at the last 5 years, our China business is growing like a 20%-plus CAGR. So I expect China to be a good business long term. There are two kinds of questions we get. One is on local development in China, there are some companies trying to write EDA tools. And second is US regulation. The US regulation is a long topic, but in summary, the impact to Cadence is pretty limited. I mean, those regulations are targeted mostly towards manufacturing in China at this point. And even if you go to China, all the big companies are not manufacturing in China, they are manufacturing in TSMC or Samsung. So we are more connected to the design activity. So now the second part is, will there be local competition in China? Because at this point, we are in a very strong position. So these things take a long time. There are some very small companies doing point tools. But to really do a full flow at 3-nanometer, of course we watch it very carefully, but I’m not concerned that this is a short to midterm issue with local competition in China. So overall, I’m pretty optimistic about the China market, yes.”

Thesis

1. Strong industry trends (increasing complexity of chips, custom silicon projects, ASIC growth, AI capex boom) that are continuing to intensify, driving LT growth of ~15-20% (above historical norms and above Street)

2. Development of AI compute / model ecosystem allows SNPS / CDNS to develop new, high-value-add deep-learning SW tools that can drive further pricing increases and capture of the semis R&D budget

Risk

1. China export restrictions / domestic competition could put meaningful % of revenue / future demand at risk

2. Valuations / expectations are high as both are favored stocks in the ongoing AI / semis trade and a slowdown in hyperscaler Capex spend would trigger a meaningful de-rating

This piece is written in collaboration with Calvin Zeng.