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The Chip Testing Bottleneck
Why AI accelerator test time has grown an order of magnitude — and how Advantest and Teradyne are turning a physics problem into a margin story.
May 8
•
Chris Zeoli
14
Why KV Cache and Memory Drive AI Economics
Behind the memory bottleneck in AI infrastructure
May 4
•
Chris Zeoli
24
1
1
The Inference Unbundling: Why Prefill and Decode Are Splitting the GPU
Different physics, different silicon, different margins. Nvidia/Groq and Cerebras/AWS are the market pricing the split.
Apr 27
•
Chris Zeoli
24
Anthropic's Compute Advantage: Why Silicon Strategy is Becoming an AI Moat
Why Anthropic’s integration into hyperscaler silicon programs may give it a lasting advantage in the economics of frontier AI.
Mar 5
•
Chris Zeoli
79
7
14
The 5 Raw Inputs Powering the AI Data Center Boom
How real estate, capital, compute, energy, and networking are the defining infrastructure inputs for the AI data center construction boom
Aug 11, 2025
•
Chris Zeoli
34
1
From Niche to Necessary: Credo’s Quiet Domination of AI Interconnects
How Credo Semiconductor became a $12B critical link in the AI data center
Jun 9, 2025
•
Chris Zeoli
10
1
DeepSeek's R1 and AI Infrastructure Economics
Did DeepSeek and its model distillation methods crush the economics of AI training?
Jan 27, 2025
•
Chris Zeoli
20
2
Broadcom's AI Infrastructure and XPU Business: Driving a Trillion-Dollar Valuation
How a strategic partnership with Google on TPUs and others on XPUs, coupled with networking, is counterbalancing NVIDIA's rise
Dec 13, 2024
•
Chris Zeoli
9
Hyperscaler AI Custom Chips (ASIC), CPUs and Networking Initiatives
Breaking down the supply chain of hyperscaler AI custom chip development
May 14, 2024
•
Chris Zeoli
13
2
ASML: The $360B EUV Lithography Equipment Giant
Highlighting the importance of ASML's EUV Lithography technology in semiconductor manufacturing and in designing AI chips
May 3, 2024
•
Chris Zeoli
5
Synopsys and Cadence: The $160B Unsung Giants of Semiconductor Design
Discussing the role of EDA in AI infrastructure and chip design
Apr 18, 2024
•
Calvin Zeng
and
Chris Zeoli
19
1
1
Astera Labs IPO: S-1 Teardown
How the newly public $10B+ semiconductor connectivity player in AI servers is changing the data center
Mar 30, 2024
•
Chris Zeoli
17
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